Code generation

VHDL

apytypes.vhdl.generate_rom(table: APyFixedArray | APyFloatArray, entity: str | None = None, address: APyFixedArray | APyFloatArray | None = None, frac_bits: int | None = None, ieee2008: bool = False, input_register: bool = False, output_register: bool = False, file: TextIO | None = None)

Generate VHDL for a ROM.

Added in version 0.3.

Parameters:

tableAPyFixedArray, APyFloatArray

The data in the ROM.

entitystr, optional

VHDL entity name.

addressAPyFixedArray, APyFloatArray, optional

Addresses for the ROM. If not provided, sequential addressing from 0 is assumed.

frac_bitsint, optional

If ieee2008 is True and address is not provided, use this many fractional bits for address.

ieee2008bool, default: False

Use ieee.fixed_pkg and/or ieee.float_pkg for the resulting ROM.

input_registerbool, default: False

If True, a register is added at the input of the ROM.

output_registerbool, default: False

If True, a register is added at the output of the ROM.

filefile handle, optional

File handle to write the file to. If not provided, a file entity.vhdl is used.